The present invention relates to a demodulation apparatus, and in particular to a demodulation apparatus for converting either a Miller-squared code signal (Miller.sup.2 signal) or the Miller code signal (modified FM (MFM) signal), which has been obtained by converting an original digital signal, into the original digital signal.
When a digital signal is to be transmitted (or recorded), it is necessary to convert (modulate) it into a digital signal having a form suited to the transmission channel (recording medium). As a signal having the above described form suited to the transmission channel, a signal with the DC component removed is known. As a signal wherefrom timing (clock) information can be easily extracted when the signal has been transmitted (recorded), the Miller-squared code signal and the Miller code signal are known.
The Miller code signal is a binary signal obtained by inverting the polarity of a serial binary signal, which is an original digital signal, at the center of the interval of each bit "1" and at a boundary between bits in case bits "0" continue.
Further, DC balance of the Miller code signal has been further improved in the Miller-squared code signal. When the original digital signal has an even number of consecutive "1"s between "0"s located at both ends, polarity inversion at the interval center of the last "1" is inhibited in case of the Miller-squared code signal.
As simple configuration of a demodulation circuit for converting the Miller-squared code signal into the original digital signal, a circuit as shown in FIG. 1 is known ("Video and Data Recording Report", 1982 IRE). As shown in FIG. 2, an original digital signal a' is modulated to produce a Miller-squared code signal b', which is then transmitted (or recorded).
The above described Miller-squared code signal b' is affected by noises. A resultant received (or reproduced) signal c' is converted to a digital signal e' in a binary decision circuit 1 in synchronism with a transmission (or recording/reproducing) clock d' and then supplied to a shift register 2 comprising four latches. The shift register 2 shifts the digital signal e' in synchronism with the transmission clock d'. On the basis of data A, B and C stored in the shift register 2, a logic circuit 3 derives a virtual demodulated signal f' by using a logic expressing shown within the logic circuit 3. At intervals of half a period of the data clock, the virtual demodulated signal f' generates a logic value "1" or "0" equivalent to the original digital signal. The virtual demodulated signal f' is supplied to a latch 4 and latched at timing of a data clock g'. Thereafter, demodulated data h' is outputted. Although two phases g' and g" of the data clock can be considered as the phase of the data clock, proper demodulation is performed by either one of them. Therefore, a proper data clock must be selected. This is uniquely defined by detecting the phase of a specific pattern i' contained in the digital signal e' such as (0111110) in a phase detector circuit 5. This is because there is fixed relationship between the phase of start of the specific pattern and the phase of the data clock. Assuming that one clock period of the original digital signal is T in case of a Miller-squared code signal, the specific pattern may have a period of 2T, 2.5T or 3T. In this example, 2.5T is adopted for the specific pattern. In FIG. 2, g' is selected as the data clock. In case the specific pattern i' is displaced before or after by one transmission clock, however, proper demodulation cannot be performed unless g" is selected as the phase of the data clock. How to define the phase of the data clock is described in detail in U.S. Pat. No. 4,027,335, for example, and is not directly related to the present invention. Therefore, its detailed description will be omitted.
In case the transmission digital signal a' is high in speed in the above described conventionally known demodulation apparatus, the shift register 2, the logic circuit 3 and the latch 4 must operate at the speed of the above described transmitted digital signal a'. Implementation of these circuits by using CMOS circuits or the like thus becomes difficult, and expensive high-speed devices such as ECL must be used, resulting in problems in LSI implementation and power consumption.